`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	DMEM_u(
    input				     clk,
    input                  rst_n,
    input                  Mem_W,
    input                  Mem_R,
    input  [7:0]      Dmem_Addr,
    input  [63:0]    Dmem_W_Data,
    output [63:0]    Dmem_R_Data
);
    reg [63:0] DMEM [255:0];
    integer  i;
    initial begin
        for (i = 0;i<=255;i=i+1) begin
            DMEM[i] = `REGD_ZERO;
        end
    end
    assign Dmem_R_Data=Mem_R?DMEM[Dmem_Addr]:`REGD_ZERO;
    always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                DMEM[Dmem_Addr]<=`REGD_ZERO;
            end
            else if(Mem_W) begin
                DMEM[Dmem_Addr]<=Dmem_W_Data;
            end
            else begin
                DMEM[Dmem_Addr]<=DMEM[Dmem_Addr];
            end
    end

endmodule